1. Field of the Invention
This invention relates to the field of data communication systems, and in particular to a device and method for facilitating communications via an I2C bus.
2. Description of Related Art
The Inter Integrated Circuit (I2C) bus developed by Philips Corporation allows integrated circuits to communicate directly with each other via a simple bi-directional 2-wire (plus ground) bus. A device connects to each of the two wires on the bus, one (SDA) for the communication of data, and the other (SCL) for the control and synchronization of the communication of data between the devices. Each device is connected in parallel to each of the other devices, and each of the bus lines, SDA and SCL, function as a wired-AND of all the lines on the bus. The output of each device is configured as an open-collector/open-drain device, and one or more pull-up resistors maintain a xe2x80x98softxe2x80x99 logic high value on the bus while the bus is in the quiescent state. When a device desires access to the bus, the device pulls the bus to a logic low value, via the open-collector/open-drain device that is placed in a conductive state to ground potential.
Each device that is connected to an I2C bus is identifiable by a unique address, and can operate as either a transmitter or a receiver, or both. Data transfers are effected using a master-slave protocol. A master is a device that initiates a data transfer and generates the clock signals to permit the transfer; any device that is addressed is considered a slave for this transfer. The data transfer can be initiated by a master to either transmit data to the slave (write), or to request data from the slave (read). A particular device can be capable of operating as either a master, a slave, or both. For example, an output device, such as a display screen, is typically not able to initiate a data transfer, and therefore would be configured to only operate as a slave device. A microprocessor, on the other hand, will typically be configured to operate as either a master or a slave, as the situation demands.
In a quiescent state, both the SDA and SCL bus lines are in the logic-high state (xe2x80x9chighxe2x80x9d). A master initiates a data transfer by asserting a transition to a logic-low state (xe2x80x9clowxe2x80x9d) on the SDA line while the SCL line is high; this is termed a START condition. Thereafter, the master toggles the SCL line to control the synchronization of the data transfer; data value changes occur on the SDA line when the SCL clock is low, and the state of the SDA line is considered valid only when the SCL clock is high. Multiple STARTs can be asserted to effect a series of data transfers within the same transfer session. Generally, each data transfer requires an acknowledgement from the addressed recipient of the data transfer. To terminate the data transfer, the host asserts a low-to-high transition on the SDA line while the SCL clock is high; this is termed a STOP condition. Thereafter, any device may assume control of the bus as a master by asserting a high-to-low transition on the SDA line, as above. Note that, for ease of reference, the term assert is used herein for effecting, or attempting to effect, the specified logic state. In the example of a transition to a logic-high state, this is typically provided by a release of the bus from a forced pull-down state by the asserting device. This assertion of a logic-high state allows the aforementioned pull-up devices on the bus to bring the bus to a logic-high state, unless another device is also forcing the pull-down state.
The general format of an I2C data transfer is illustrated in FIG. 1, which illustrates the signals on an SDA line and an SCL line forming the I2C bus. A START condition (S) is illustrated at 110, corresponding to high-to-low transition of the signal on the SDA line while the SCL line is high. After the START, the host transmits an address 120, nominally seven bits, followed by a read/write-not indicator 130. After transmitting the address 120 and the direction of data transfer (R/W-) 130, the host releases the SDA line, allowing it to rise to a logic-high level. If a slave device recognizes its address, the slave device transmits an acknowledge signal (ACK) 140 by pulling the bus low. The absence of a low signal when the host releases the SDA line, therefore, indicates a non-acknowledgement (NAK). If the address 120 is acknowledged, via a low at 140, the transmitting device transmits the data 150. If the direction of data transfer is a xe2x80x9creadxe2x80x9d relative to the host, then the slave device is the transmitting device; if the direction is a xe2x80x9cwritexe2x80x9d relative to the host, then the master device is the transmitting device. The transmitting device releases control of the SDA line, and the receiving device acknowledges the receipt of the data 150 by asserting a logic-low value on the SDA line, at 160. If the data is acknowledged, the transmitter sends additional data 170. This process continues until the entirety of the data is communicated, or until a transmitted data item is not-acknowledged, as indicated at 180. The master can subsequently reassert a START signal (not illustrated), and repeat the process above, or, can assert a STOP signal (P) 190 to terminate this data-transfer session.
The above interface protocol can be implemented in a variety of ways. To minimize the development time for programming or designing an I2C interface, a variety of general-purpose interface schemes have been published. xe2x80x9cDESIGN OF A BEHAVIORAL (REGISTER TRANSFER LEVEL, RTL) MODEL OF THE INTER-INTEGRATED CIRCUIT OR I2C-BUS MASTER-SLAVE INTERFACExe2x80x9d, Master""s Thesis of Amrita Deshpande, University of New Mexico, 1999, discloses an I2C master interface and slave interface that is intended to be embodied in an I2C device, and is incorporated by reference herein. By providing a verified I2C interface, system designers need not address the details of the I2C specification and protocol. Both the master and the slave interfaces of this thesis are state-machine based.
A state-diagram 200 corresponding to the I2C slave protocol of the referenced thesis is illustrated in FIG. 2. The state diagram 200 comprises six states, A-F, and state transitions are effected on the active edge (0-to-1 transition) of the SCL clock signal from the master. That is, in accordance with the I2C specification, the master controls the sequence and synchronization of operations on the bus by controlling the SCL clock line. A slave device must operate in synchronization with the master device, such that transitions on the SDA line only occur while the SCL line is low, and such that valid data is present on the SDA line for the duration of the high state on the SCL line.
A reset signal, typically a power-on reset, brings the interface to state A, the idle state. When a START condition is detected, the interface enters state B, where it receives the aforementioned (FIG. 1) address 120 and data-direction 130 information from the host. If the received slave address does not match the address associated with the particular interface 200, the interface returns to the idle state A. If the data-direction 130 is read, the interface enters state C; otherwise, if the data-direction 130 is write, the interface enters state E. When the interface enters state C or state E, it acknowledges the receipt of its address and the data-direction, and prepares the interface for the required read or write operation. As noted above, the read and write directions are relative to the master device. Therefore, at the slave device, a read corresponds to a request for the slave to transmit data to the master for reading, and a write corresponds to a request for the slave to receive data written from the master.
In state C, the data that is to be transmitted to the master is loaded, and the interface transitions to state D, wherein it transmits the loaded data to the master. If the master acknowledges the receipt of the data, the interface re-enters state C; otherwise, it re-enters state A and awaits another start condition. Generally, the master controls the amount of data received by communicating a not-acknowledged (NAK) signal to the slave when the last desired data element is received, thereby returning the slave to the idle state, A.
In state E, the location at which the received data is to be stored is cleared, and the interface transitions to state F, wherein it receives the data from the master. After receiving each data item, the interface sends an acknowledge signal, and transitions back to state E to receive the next data item. If the slave device is unable to receive the data from the master, it asserts a non-acknowledged signal to the master, thereby terminating the current data-transfer session, and transitions back to the idle state A. If the master asserts another START condition, the interface returns to state B; otherwise, if the master asserts a STOP condition, the interface returns to the idle state A, to await the next START condition.
The prior art state diagram 200 implements the I2C-bus specification, and therefore can provide a standard interface for an I2C device by providing a state machine that embodies the state diagram 200. The functional element of the I2C device, such as a processor, a memory element, a display device, etc., need only provide the data that is to be transmitted, at state C, to the state machine, or provide a memory space for receiving the data that is to be received, at state E, to the state machine. In this manner, the designer of a functional element of the I2C device need not be concerned with the details of implementing an interface to the I2C-bus. For ease of reference, the term state machine 200 is used hereinafter to refer to a state machine that embodies the state diagram 200.
Although the prior art state machine 200 implements the I2C-bus specification, it has a number of limitations. As noted above, the I2C specification requires that the master device control the timing on the I2C-bus. A well-behaved master in an ideal environment will effectively control the state machine 200 in a slave device to effect the I2C-bus interface, but a poorly-behaved master, or a non-ideal environment, has the potential of locking-up or otherwise adversely affecting the operation of the prior art state machine 200, and potentially affecting the operation of the entire I2C-bus. For example, if a master ceases to toggle the SCL line, due to a problem in the master, or an unintentional disconnect, while the state machine 200 is in state D, the transmit-data state, the state machine 200 will remain in state D. When another master initiates a new transfer session, via the assertion of a START condition, and then toggles the SCL line, the state machine 200 will merely continue where it left off in state D, and will transmit its next bit while the other master is transmitting the address of the intended slave of its transfer session. Thereafter, the state of the I2C-bus, the state of the state machine 200, and the state of the other master will be indeterminate. The other master will likely recognize the interference and xe2x80x9cback-offxe2x80x9d, but when it, or yet another master, attempts to communicate after asserting another START signal, the problem will recur. The problem continues until the state machine 200 transmits all of the data bits of its current data byte, then detects a high state on the SDA line at the next active SCL period, and returns to the idle state A. If the state machine detects a low value on the SDA line at the next active SCL period following the transmission of its last data bit, it will interpret this as an acknowledge-signal, will re-enter state C, load the next byte, and continue to transmit each of the bits of this new byte at each SCL transition. Other scenarios of potential problems can be formulated for other occurrences of anomalies on the SCL line while the state machine 200 is in other states, as well.
It is an object of this invention to provide an apparatus and method for robustly controlling an interface to an I2C-bus. It is a further object of this invention to provide an apparatus and method for avoiding inappropriate and/or interfering transmissions on an I2C bus. It is a further object of this invention to provide a recovery mechanism for a slave device on an I2C bus after anomalous master-device behavior.
These objects and others are achieved by providing a robust state machine that controls an I2C-bus interface. The state machine is configured to enforce the slave-device-protocol of the I2C specification, and to provide recovery from anomalous master-device behavior. In accordance with this invention, the state transitions of the state machine at the slave-device are controlled by the master-device""s control of the SCL line of the I2C-bus, except if a START condition is detected. The state machine is configured to asynchronously respond to a START condition on the I2C-bus, regardless of its current state, to force the state machine to a known state. In the known state following the START condition, the slave-device terminates any transmissions to the I2C-bus, thereby minimizing subsequent interference on the bus.